Do We Need a Quantum Computer?

Above: the strange Qbit portal that is neither an exactual representation of computing zeros or ones is a red hot phantasmic-appearing quantum computer that can open the door into an alternate reality of ultra-computing power that must be continuously quantum-cooled to cryogenic space-environment levels

Do We Need a Quantum Computer?
The Big Brain Technologies Board of Directors is contemplating the acquisition and/or manufacturing of a quantum computer for the purpose of a new brain for AI artificial intelligence far reaching projects. This quantum computer could be fashioned into the next artificial intelligence brain for implantation into human society. It could also solve problems in a minute that currently take conventional computers a hundred to one thousand years to complete, vastly dissolving the wake of present-day slow-by-comparison supercomputers.

For over ten years, Big Brain Technologies has remained on the cutting edge of scientific exploration. After the completion of the Android / TransHuman / Augmentation project of converting a human into the symbiosis of an AI machine, the Board of Directors is looking towards a series of far reaching projects and examining the methodology and advanced technological tools required for such grand exploratory endeavors. A Quantum Computer is at the doorstep to moving into the next millennia of our future. Stay tuned to the results of the next meeting to ascertain the exciting pathway to our future.

Quantum computing is a type of computation that harnesses the collective properties of quantum states, such as superposition, interference, and entanglement, to perform calculations. The devices that perform quantum computations are known as quantum computers. Quantum computing is a rapidly-emerging technology that harnesses the laws of quantum mechanics to solve problems too complex for classical computers. Quantum computers perform calculations based on the probability of an object's state before it is measured - instead of just 1s or 0s - which means they have the potential to process exponentially more data compared to classical computers.

Quantum computing is a new generation of technology that involves a type of computer 158 million times faster than the most sophisticated supercomputer we have in the world today. It is a device so powerful that it could do in four minutes what it would take a traditional supercomputer 10,000 years to accomplish. 

The Ramifications of Machine Thinking Time Frame
Machine Thinking Time Scale

Machine Time        Human Time
.5 second                16 years
1 second                 32 years
4 seconds              128 years
10 seconds            320 years
1 minute             1,920 years
10 minutes       19,200 years
1 hour            115,200 years
1 day           2,764,800 years
1 week      19,353,600 years
1 year  1,006,387,200 years

https://humanoidolabs.blogspot.com/2020/04/the-danger-of-ai-by-humanoido-big-brain.html

First Human Machine Brain Size

As shown in this illustration, the first human brain converted to a machine brain may take up
every floor of an entire skyscraper and demand a small team of operations specialists. Due to
the number of machine pathways using current computer technology, the space required is more
than massive. This calls for extreme measures and a solution to decrease machine brain size.

First Human Machine Brain Size
The first full human brain to be placed into a machine may take up the space of an entire skyscraper!

Based on the human brain calculus conversion to a machine brain, the number of neurons and synaptic pathways are enormous, so much that it could fill a machine the size of a skyscraper. What are some methods and solutions to temper the machine brain size that holds a complete uploaded human brain?

Increase the Technology
Undoubtedly, a way must be found to temper and put restrictions on the size. One way of doing this is by jumping the technology level by an exponential amount. To do this may require the next step in quantum computing. Another idea is to place the structure completely into a virtual brain cloud.

Reduction Algorithms
Another method is by machine reduction using software and hardware algorithmic processes for the reduction of data, but this technique must remain as fast as possible without any noticeable slowing in bandwidth.

Alter the Machine Brain from the Human Standard
Can the human brain transfer to an artificial machine brain that is unlike the human brain but can host and serve all of the human brain functions? This may allow for a dramatic size reduction and offer ways to speed up functions.

Neurons and their Connections
The average human brain has about 86 billion neurons (or nerve cells) and many more neuroglia (or glial cells) which serve to support and protect the neurons. Each neuron may be connected to up to 10,000 other neurons, passing signals to each other via as many as 1,000 trillion synaptic connections, equivalent by some estimates to a computer with a 1 trillion bit per second processor. Estimates of the human brain’s memory capacity vary wildly from 1 to 1,000 terabytes. For comparison, the 19 million volumes in the US Library of Congress represents about 10 terabytes of data.

Memory Storage Capacity
Most computational neuroscientists tend to estimate human storage capacity somewhere between 10 terabytes and 100 terabytes, though the full spectrum of guesses ranges from 1 terabyte to 2.5 petabytes. One terabyte is equal to about 1,000 gigabytes or about 1 million megabytes; a petabyte is about 1,000 terabytes.

TSS Tiny Stamp Supercomputer

Tiny Stamp "Supercomputer" TSS
The World's 1st Hand-Held BASIC Stamp "Supercomputer"
 
by Humanoido

This is the TSS Tiny Stamp Supercomputer that appeared in Robot Magazine.

In the January/Feb. 2011 issue of Robot magazine, page 16 in the LERN section you saw the BASIC Stamp Supercomputer. This is actually the new portable project TSS - Tiny Stamp Supercomputer that uses seven cores and a BELKIN USB HUB. In the same issue of Robot magazine, you can see two more articles about robot humanoids in China.

(demonstration of basic principles to take some characteristics of a supercomputer, in particular the notion of larger multiples of relatively simple processors communicating over a common bus, each doing a portion of a task in parallel)

The BASIC Stamp Clustered Supercomputer series is a number of hobby projects to design BASIC Stamp microcontroller clusters with more power compared to a single Stamp. The name supercomputer is indicative of the increase in power by comparing to a single stamp.

Absolutely the most powerful in terms of the smallest footprint with many tiny Stamp networked processors. It’s a cluster of Stamps in your hand. Has its own book with 30 fun projects. Includes Architecture, Assembly, Programming, Tutorial, Applications, Complete Code. The TSS has multiple computers, LCD monitor, radio transmitter, receiver, speakers, breadboard real estate and a 64K EEPROM memory board, all interfaced to a tiny Hub. The TSS Stamp supercomputer is so small it will fit into a soup bowl or coat pocket. Includes special features such as hardware programming "on the fly."

The Tiny Stamp Supercomputer (TSS) is the first hand-held Basic Stamp Supercomputer. It’s the smallest in the series of Parallax Basic Stamp supercomputer projects by Humanoido. It is also the first USB Stamp supercomputer, made possible by the innovative BS1USB board made by Parallax. This project compliments the Basic Stamp Supercomputer (BSS), the Stamp Baby Supercomputer (SBS/Baby), and the Propeller (MELS) supercomputer.

Price & Disclaimer
This is a pure hobby project for my personal enjoyment and use only, and is not for sale. If the project does not satisfy your requirements, keep in mind that it was not intended to do so. This is not a product, and the descriptions are offered as is, in whatever degree or lack of degree of completeness for your inspiration and ideas. Good luck!

ABOVE: This is a view of the new “hand-held” Tiny USB Stamp Supercomputer TSS during construction. Seven computers, LCD monitor, radio transmitter, receiver and a 64K EEPROM memory board are interfaced to a Belkin USB Hub. The Stamp supercomputer is so small, it will fit into a soup bowl or Parka coat pocket. The yellow wires are for the port-to-port one wire interface. The black wires are adjoining Vss and red wires are Vdd. White represents a serial signal wire. By comparison, the American penny shows the extreme tiny features of the TSS Tiny Stamp Supercomputer! 

Tiny includes an optional serial “green screen” by Parallax, pulling a whopping 20ma, the most power hungry device in this ultra tiny array. This is actually a miniscule power draw. In fact, the supercomputer consumes so little power, it would be a good candidate for solar power. Note the position of two computers located in the front behind the LCD. The remainder computer array is located to the rear of the USB hub.

How to Build Tiny - Building Up the USB Hub First build up the USB Hub by attaching three small solderless breadboards using their self adhesive sticky tape on the back side. Locate the breadboards according to the photo. Each breadboard side has 17 rows of 5 pins for 85 holes to a side, giving a total of 170 holes perboard. This makes a total of 510 wire and component mounting positions with all three breadboards. The hub has eight lights (one red power light and seven green LEDs indicating connected USB devices). The USB Basic Stamps have seven green LED lights indicating power on status. Tiny has a total of fifteen status lights.

Tiny is a powerful array of seven BS1USB computers connected to a Belkin HI-Speed USB 2.0 powered 7-port Hub. The 7-port Belkin Hub’s advantage is its ability to provide considerable power to the USB devices (Stamps) simultaneously, and peripherals, not drawing from the laptop’s limited power source. Each tiny Stamp PCB contains vital components (processor, clock source, memory, power regulator).
Tiny packs a punch in a small package and is loaded with features and peripherals. Let’s take the grand tour!

Affixed to the high speed USB hub are seven Parallax BS1USB computers, seven piezo speakers, a Parallax 433 Mhz radio transmitter, a matching receiver, Parallax serial LCD green screen monitor, eight pushbutton keypad, DS1620 Digital Thermometer, Parallax EEPROM non-volatile memory board, and a Parallax QT113-D Touch Sensor. Tiny can access other Stamp Supercomputers located within a full city block, communicate with a Base Station, and cluster together entire Stamp supercomputers located around the city!

The Tiny Stamp Supercomputer blueprints show schematics for the base unit. This contains seven clusters of BS1USB computers interfaced to a powered USB hub for programming. After all seven computers are programmed, the USB cable from the Hub to the Laptop is removed. The wall power supply to the hub remains on. Compare the new Tiny Stamp Supercomputer blueprints (seven computers) with the networked 3D Stamp Computer (three computers).

Historically, the 3DSC is the forerunner of Tiny, and the first 3DSC Stamp clustered array to incorporate the BS1. The BS1 is filled with advantages, in terms of tiny power consumed, tiny footprint, large number of ports, and large capabilities for more powerful hobby BASIC Stamp clustered machines.

Wiring & Assembly Step by Step
Wiring is accomplished from port to component and component to port using the computer’s on board SIP socket and small gauge wire, plus the three small Parallax solderless breadboards attached to the Belkin Hub housing. This will support numerous additional supercomputer components and sensors.

( ) Plug in seven BS1USB computers to the Belkin 7-port hub
( ) Run a wire from P0 Computer 1 to P0 on Computer 2. Repeat to Computer 7.
( ) Connect all grounds together with jumper wires (Vss)
( ) Connect all +5 volts together (Vdd)
( ) Consult the schematic to wire the peripherals

Tiny Stamp Supercomputer Parts List
Parts for the Main Supercomputer
7 - Parallax BS1USB Board
1 – Belkin Powered High Speed USB 2.0 Hub
3 – Parallax Solderless Breadboards
4 – Rubber Bands
30 – Pin to Pin Jumper Wires
Peripherals Used in this Project, from Parallax
7 – Five Volt Piezo Speakers
1 – Green Screen Serial LCD
1 – 433 Mhz Radio Transmitter
1 – 433 Mhz Radio Receiver
1 – 64K EEPROM Memory Board
Parts for Project Applications
1 – Low Power Parallel LCD
1 – Temperature Chip DS
1 – Capacitor .1uf
1 – Touch Sensor QT113
1 – 470 Ohm Resistor
1 – LED
10 – Toggle Switches
10 – 1K Ohm Resistor
7 – 220 Ohm Resistor

APP 22
CaS Cell
Capacitor .1uf

Wiring “On the Fly”
A unique feature of TSS is that it can be wired and rewired as you are moving from one location to another. It’s a portable wiring feature that enables much more function due to simple access of its circuits.

Test Software for Each Computer
The test program loads into each of the USB stamps. When running the clustered code, after each stamp is programmed, the USB cable can be disconnected and the hub is removed from the laptop. All computers will remain powered on and functional.

' {$STAMP BS1}
' {$PBASIC 1.0}
DEBUG "hello world"
END

Test Software for the Cluster Interface
Test software for networking the cluster is seen below. This code includes timing routines. Each computer sleeps a designated time period and wakes to perform a task.

Loading in Code to Seven Computers
When loading a program, the menu appears to select any one of the seven Basic Stamps. Simply click on the desired computer, 1 through 7, and the code will load. This process is the most simple of all the Stamp/Propeller supercomputers.

Use this as a wiring guide to each pin. Note the actual configuration for each computer mounted on the USB Hub is inverted from this photo.

SOFTWARE
Loading code into each computer is a very simple process. Wait for this window to appear and select the stamp to receive the code.
 

The BS1USB is tiny, measuring only 2.26-inches long, .73-inch wide and .3-inch thick. Right: the back side of each board has a legible pin code printed in white.

Features

• 7 Computers (BS1USB)
• Fifty-Six Ports (configurable as inputs or outputs)
• Each Computer 2.26-inches Length x .73-inch Width x .3-inch Thickness
• Overall Stock Supercomputer 4 ¾ wide x 4 ¾ deep x 2 ½ height
• Each I/O pin sources 20ma and sinks 25ma
• All I/O pins on one computer can source 40ma and sink 50ma
• Each Computer has an on-board USB interface
• Two Vss, Two Vdd and eight pin I/O connectors
• 7-Port Belkin High Speed Powered USB 2.0 Hub
• Memory: 64K Serial EEPROM Memory Board
• Two Thousand Four Hundred Bits Per Second Transfer Rate

 
Single Processor Specifications

• Microcontroller PIC16C56a
• Processor Speed: 4 MHz
• Program Execution Speed: ~2,000 PBASIC instructions/sec.
• RAM Size: 16 Bytes (2 I/0, 14 Variable)
• EEPROM (Program) Size: 256 Bytes; ~80 PBASIC instructions
• Current Draw @ 5 VDC: 1mA Run, 25 μA Sleep
• Number of I/O Pins: 8
• Source/Sink Current per I/O: 20 mA / 25 mA
• Source/Sink Current per unit: 40 mA / 50 mA
• PBASIC Commands: 32
• PBASIC Language: v1.0
• Scratchpad RAM: n/a
• PC Interface: USB
• Windows Text Editor Version: Stampw.exe (v2.0 and above)
• Breadboard Area: 1 3/8 x 2" solderless breadboard or through-hole mounting pads

 
Seven Processor Specifications

• Seven Cores
• Core Speed 28Mhz
• Program Execution Speed: ~14,000 PBASIC instructions/sec.
• RAM Size: 112 Bytes (14 I/0, 98 Variable)
• EEPROM (Program) Size: 1,792 Bytes; ~560 PBASIC instructions
• Current Draw @ 5 VDC: 7mA Run, 175 μA Sleep
• Number of I/O Pins: 56
• Techniques for 448 inputs, or 112 I/Os
• Source/Sink Current per I/O: 20 mA / 25 mA
• Source/Sink Current per unit: 40 mA / 50 mA
• Source/Sink Current per supercomputer I/O: 280 mA / 450 mA
• Breadboard Area: about 14 by 20”

 
Comparative Speed to the Cray 1 Supercomputer
Don’t expect too much speed compared to the worlds fastest supercomputers today or even desktop computers! This is a small hobby supercomputer and is super in terms of comparison to one Stamp in the same genre.

If you want to convert the actual speed to OPS, operations per second, a chart will illustrate the example. The SBS runs at about 20,000 IPS (instructions per second). FLOPS is floating point operations per second. Grossly approximating IPS to FLOPS, the SBS is about 20 kiloFLOPs or one fifth of a megaFLOP (MIP). By comparison, the Cray 1 supercomputer was in the MIPs range (millions of instructions per second). So one could roughly say the SBS is only approaching the speed of the Cray supercomputer.

Expansion Peripherals
The Tiny Stamp Supercomputer can be expanded with these low power peripherals:

Expansion Peripherals Computer Ports Used Each Power (ma)

• Computer 1 N/A 1ma=run, 25ua=sleep
• Parallax LCD 2x16 1 1 20
• Memory Board 7 1 10
• 433 Mhz Radio Transmitter 3,4 1 10
• 433Mhz Radio Receiver 3,4 1 5.2
• One Port 8-Pushbutton Keypad 2 1 5.0
• Touch Sensor 6 1 1.5
• DS1620 Digital Thermometer 5 3 1.0
• Piezo Speaker 1-7 1 1.0

 
7-Port Belkin High Speed Powered USB 2.0 Hub Specs

• Upstream Ports 1
• Downstream Ports 7
• Per-port Voltage DC +5V
• Per Port Current 500mA (max)
• Power Mode Self Powered (AC Power Adapter)
• Operating Temp 5deg ~ 40deg C
• Storage Temp -20deg ~ 60deg C
• Enclosure ABS
• Power Supply Output: DC 5V, 3.8A
• Plug Size: 3.5mm outer, 1.0mm center
• Plug Polarity: Center Positive
• Red Power LED Off Not Operational
• Power Status LED Green Fully Operational, Off Over-current Condition

Compliant with Universal Serial Bus Specs 2.0, data rate 1.5/12/480 Mbps, backwards compatible with USB spec 1.1 data rate 1.5/12 Mbps, Win 98SE, Me, 2000, XP, supports plug and play, and hot swapping, approved by USB Implementers Forum (USB-IF), over-current detection and protection, individual port status indicator LEDs, five horizontal mounted 480 Mbps downstream ports, two vertically mounted 480 Mbps downstream ports, fully compatible with USB 2.0 and 1.1 devices, compact slim-line design, two hubs may be stacked on top of one another, also Mac enabled – see operating manual for more details.

One Wire Interface The Stamp supports an open baud mode that switches to +5 volts dc only instead of ground. This is the open-source configuration, selected by an argument beginning with ON, such as ON2400. The 1K ohm resistor goes to ground.

Compare the size of these BASIC Stamp Supercomputers with the TSS. From left to right, the BSS Basic Stamp Supercomputer, SEED Supercomputer, and Tiny Stamp Super Supercomputer TSS.

Interesting Comments

USB Computer Ports
You might think it's possible to plug three USB Stamp boards into your computer's USB ports and begin clustered computing. Not possible with most computers. The sum current draw exceeds the amount of deliverable power from the combined USB ports on the PC computer. A powered Hub is needed to remedy this by supplying full power to all USB Stamp boards.

Non-Powered USB Hubs
You might think it's possible to just plug multiple USB Stamp boards into any USB hub and computing is possible. Not possible. A powered hub will be needed. You can try one or two Stamps in a non powered hub, but with 3 or more it is likely to exceed pc power capacity.

Powered USB Hubs
Even with some non-powered USB hubs, there is an incompatibility with some brands. Even a Belkin non-powered hub will not drive three or more Stamps.

Schematic Center

Check out the hi-res version of this rare BS1USB Schematic in the PDF file (download as seen below).

BS1usb_sch.pdf‎ (112.8 KB, 1219 views) 

SOFTWARE
==============================================
A Snoozer Program to put individual cores to sleep for ten seconds, then do a wake-up call based on a pause statement.

' {$STAMP BS1}
' {$PBASIC 1.0}
Snoozer:
DEBUG CLS, "Sleep for 10 seconds"
SLEEP 10 ' Sleep for 10 seconds
DEBUG CLS, "awake now!"
PAUSE 1000 ' Awake for a second, or set timing here
GOTO Snoozer

==============================================
The standard Hello World program is a good first test for each core.

' {$STAMP BS1}
' {$PBASIC 1.0}
DEBUG "hello world"
END

==============================================
Determine memory used by a PBASIC Program
Use this code to determine memory consumed by a PBASIC program. On the BASIC Stamp I, enter the following code at the start of your PBASIC1 program:

'***MEMORY USED***
READ 255,B0
DEBUG #B0
' ****************

Upon running the program, a number will display in the debug window of the editor. Use the following equation to determine how many bytes are used by your PBASIC1 code: 255 - # - 6; where # is the number displayed on the debug window. Note, the “- 6” in the equation results from the fact that the above two lines of code take 6 bytes of program space, thus without those two lines, your program takes 6 fewer bytes of space. 

Cores, Parallelism, Determinism
The little TSS machine has seven cores which is numerically defined by the Belkin HUB. As a purely academic comparison, the TSS can use all seven cores at the same time in parallel, with true determinism. This aspect is similar to a Propeller chip's eight cogs.

 

In this particular fashion, Propeller cogs can be simulated or emulated on a simple level. The TSS has huge robotics potential for controlling numerous sensors at the same time. Cores can operate servos while the vision center can continue to function, for example. If you have some of these tiny BS1USB boards handy, this is one way to find a good use for all the processors with this simple project.

In the TSS, seven of BS1 USB boards connect to a powereed HUB. Small pin connectors are enough for wiring when combined with several tiny solderless breadboards. Dimensions of this board are: 2.25 x 0.75 x 0.35 in (5.72 x 1.91 x 0.89 cm).

 

Running Core Software
============================================== Serial Communications programs are in the Handbook of BASIC Stamp Supercomputing.

This PBASIC code sets up the Master-Slave concept and establishes Talk/Listen rules for simple communication.
============================================== TinyAI is found in the BASIC Stamp SEED Supercomputer post (runs on ten cores).

PBASIC code utilizes ten cores to set up AI. The same program loads into each core and evolves. Requires ten deterministic pin circuits. The schematic is written in the software comments. In the code, remove three processors to run on the TSS.
============================================== TinyAI for the TriCore is found with the BASIC Stamp TriCore Supercomputer post (runs on 3 cores).

This code is written in PBASIC and utilizes three cores to set up AI. The same program loads into each core and evolves. Requires three deterministic pin circuits. The schematic is written in the software comments. In the code, add 4 processors to gain the total of 7, or run as is on the TSS using 3 processors, as a sample program.
==============================================

ANNOUNCEMENT
This is to announce the hobby TSS Tiny BASIC Stamp Supercomputer and update the family list of BASIC Stamp supercomputing machines.

The TSS is number SEVEN out of seven BASIC Stamp Supercomputers and Stamp Computing Machines. BASIC Stamp Supercomputers now include the following family. For links, refer to the signature.

BSS - BASIC Stamp Supercomputer SEED - BASIC Stamp SEED Supercomputer TRICORE - Three Cores MINUSCULE - Minimal Two Core Machine TSS - Tiny BASIC Stamp Supercomputer MOM - Master Offloader Machine TWO STAMP BSS (BS2sx + BSpx) AM - The Algorithm Machine

The Grapevine Speculation
Will there be another BSS? Considering that the BSS family and its spinoffs now encompass almost all BASIC Stamp boards and modules, it is possible that the torch may pass on to the Propeller chip. The question is, are there any new Stamp boards or modules that could be utilized in future projects that would show some new features? There is some thought about making a "super stamp" out of a Propeller chip. The Super Stamp would have the extra memory and speed (+cogs) of the prop, yet program in BASIC and have PBASIC functions and a similar module form factor. There is some discussion about using the SPIN Stamp for this purpose. One idea is moving towards more cost effective multiplicities. The propeller chip is about $1 per computer and this remains highly competitive. So what is coming up? You will begin to see some enhancements for modules and chips that can be applied to the BASIC Stamp and the Propeller chip, as well as dedicated supercharged machines.

AUTHOR COMMENTS
The education that I get from these supercomputers is the greatest value and it continues. The Basic Stamp Supercomputer is the first in a continuing line of similar projects with additional features and strengths. I consider each project to be a step on a ladder, reaching upwards towards a higher plateau of evolution. With each, there's testing and designing of new circuits and new software, and I do my best to make the details and plans available to everyone to hopefully have as much fun as I have and share in the information.

I began avidly putting multiple Stamps together back around the year 2002, to create a kind of bigger and better brain for humanoid robots. I recall experimenting with two to four connected Stamps to gain added ports and extended software commands and do serial control of servo motors. My overall goal was to create a giant brain that could power humanoid robots. The plan was to use upwards towards hundreds of BASIC Stamp processors!

I am still on the learning path of more powerful super computers, and have another BASIC Stamp version in the works that's very unique and useful. I have also progressed to the Propeller chip with eight cores. You have to blame those guru dudes on the forum for egging me on to start with the prop. They have caused such a propeller passion that consumes all my time! :)

You can read about the Propalot saga in "Propalot Stuff." It describes the continuing evolution of connecting together ten Propeller chips on a breadboard to create a tiny little paralleled cluster. This cluster is evolutionary from my viewpoint - containing 80 computers and 320 controlling ports, running at up to 2,000 MIPS. That's two billion instructions per second in a space the size of your dinner plate. The uses are learning, fun, trying out various designs, experimenting, wiring up hardware, learning SPIN and other languages, programming various effects, etc...

Another surprising benefit of the BSS and SEED supercomputers is that they bring new friends. Nearly every week, someone requests that I run one of the supercomputers through its paces. Of course the talking BSS is very impressive to my Chinese friends, because it's programmed it to speak in Chinese. But I must say, the SEED supercomputer, is loved by everyone. They enjoy watching the life forms evolve and to see their responses on the debug screen (such as getting to know the neighbors, memorizing, reciting, napping, sleeping, working, etc.) Each of the ten processors have a little beeping piezo speaker and we all know they are talking back and forth to each other in some kind of binary code.

One time, the program finished and about 10 minutes later - suddenly- they started beeping to each other. Your guess is as good as mine... I have no idea what they were talking about... (the program had become too big and some parts were overwritten and it took on a mind of its own)

 

40 Props in a Skyscraper - UltraSpark 40

Smart Boebot brain app

40-Prop SkyScraper Computing Machine
UltraSpark 40 - Super Microcontroller
A Propeller project with 40 prop chips providing 320 RISC computers with 1,280 ports and 6,400 to 8,320 MIPS speed.

DOCUMENTED FROM JULY 10, 2010
(demonstration of basic principles to take some characteristics of a supercomputer, in particular the notion of larger multiples of relatively simple processors communicating over a common bus, each doing a portion of a task in parallel)

This is a simple hobby project designed for pure fun and enjoyment! It may be the most fun project I've ever worked on (cool toy). I only started with the prop about 2 months ago. Thanks to everyone on the forum who posted helpful comments as I learned more SPIN and elements of assembler code. Also thanks to those addicted prop-heads who convinced me to take a look at the Propeller chip. I took a look and this is what happened. It's all your fault!

EDIT: the US40 has become a much more massive project taking several turns of development. It is being used primarily now for Academics. Additional posts underscore continuing developments.

Photo montage shows various views of a simple multiple Propeller chip ongoing project. It will morph into various configurations as new circuits are tested.

Price & Disclaimer
This is a pure hobby project for my personal enjoyment and use only, and is not for sale. If the project does not satisfy your requirements, keep in mind that it was not intended to do so. This is not a product, and the descriptions are offered as is, in whatever degree or lack of degree of completeness for your inspiration and ideas. Good luck!

Form Factor
The UltraSpark 40 easily fits onto a desktop with its small form factor. The space between the Proto Boards is reduced using smaller 5/8-inch spacers. For size comparison, the IBM ThinkPad is the black object under the SkyScraper.

SkyScraper (Tower)
The first Skyscraper took on this shape using 20 Parallax Proto Boards and nylon spacers to achieve a minimal 5/8" board-to-board spacing. Spacing is determined by the vertical height of the board's 1000uF electrolytic capacitor. The SkyScraper has three sides of the board supported. The open end allows more easy routing of wires and cables (not shown in these early pics).

UltraSpark 40 Specifications
40 Props DIP Mix with SMT, Model Number: P8X32A-D40
320 Tiny RISC Computers
Processor/cog/small risc computer Per Chip: Eight
Architecture: 32-bits
Math: Integer and Floating Point
Standard System Clock Speed: DC to 80 MHz
Overclocked to 100MHz
Global RAM/ROM: 40x64 K bytes; 40x32 KRAM / 40x32 KROM
Cog RAM: 512 x 32 bits each x 320 cogs
1,280 ports
640 Counters
20 Dual Expanded Proto Boards with SMT Props
20 Socketed Prop DIPs
Hypered Stack Configuration
Socket Twins Concept
6.4 Billion IPS Standard (Instructions Per Second)
(40 props * 8 cogs * 20 mips = 6,400 MIPS, 6.4BIPS ~= 64MFLOPS)
8.32 Billion IPS Overclocked
(40 x 8 cogs x 26 mips = 8,320 MIPS. 8.32 BIPS ~= 83.2MFLOPS)
Computer Programming Languages approaching 200
Open Ambient or Compressor Cooling
Tiny Parallel Architecture
Computing Array: Parallel Clustering
IEX Technology Endowed
Ext PS Enabled
EEPROMs for Programming, Indexing
Reconfigurable Whole Cubes up to 6 x 6 x 6
Video 3.5-inch TFT LCD AV 4:3 Panel NTSC/PAL 320 x 240 Pixels 12V 3.5W

Terminals
Prop Terminal + special version of FemtoBASIC

Emulation
Emulators: TV, Mouse, and Keyboard

Compatibility/Expansion
HW Proto Boards
HW HYDRA
HW Propeller Demo Board
SW Prop Terminal (virtual keyboard, TV, mouse & keyboard)
SW Digital Storage Scope
OIT (Optics Interface Transceiver)
P-BUS (Prop BUS)
DEEPROM (Dual-EEPROMs)
FLEXPANDABLE (upward mobility path)
SIGNAL ROAMER (not confined to boards)
SKYSCRAPER Expanding F1, F2, F3 ... or B1, B2, B3 ...
Testing Various Designs
Multi-Interface MINT encompasses the chip to chip communications
Circuits for downloading one program into all the props (bootloader)
Path for maintaining 'across the Skyscraper' critical timing
Special oscillator to handle all mult props
Nominal RFI/EMI blanket shield
What is it for?
Hobby only (fun)
Pure Academics
Robots, Robot Control, Sensors
Education, Schools, Students, Educators
Tiny & Simple Parallelism Exampling
running benchmarks
new programming
developing new parallel programming languages
developing & testing new circuits
running many different programming languages
new experiments
exploring capability of 320 little computers running at the same time
developing new apps
robot brain
testing
multi-games
pushing the limits
testing and developing a small neural net
solving codes
New Algorithms
Currently an interest has developed in parallel and various algorithms which has led to some very interesting experiments and results.

Software & Wiring Criteria
Wiring is simplified
Wiring is easily changeable
Speed is maximized for the interface used
Interface facilitates loading all props at the same time
Interface handles frequency synchronization
Code handles identifications
Minimal power consumption is implemented
Interface is compliant with parallel programming and code
Wiring Real Estate Provided
Parts/Circuits are green configured

Software Download
Current software is available and can be downloaded at the Parallax Propeller OBEX. The UltraSpark 40 is a flexible machine and not confined to one design. However, if you want to duplicate the first fundamental design, most of the single wire serial interface drivers will work.

Schematic Download
The schematic that I used is the same as the BASIC Stamp Supercomputer and can be downloaded at that thread. A modification to the value of the resistor may be needed.

Hardware
The first setup included a wire bus in Daisy Chain mode that threaded all of the prop boards through pin 0 and the twin prop. Wire wrap technology is used because the twin prop can be removed and the board will be available for other configurations and recycling into larger projects. A front end prop experiment (one HYDRA) provides TV, Keyboard, game controllers, VGA, mouse, and numerous more capability.

Concept
There are two concepts for communicating internally - 1) the Master/Slave technique and 2) the deterministic approach. More information and examples are provided in the Handbook of BASIC Stamp Supercomputers. The BASIC Stamp Supercomputer uses the Master/Slave approach while the SEED Stamp Supercomputer uses Tiny AI. The UltraSpark 40 can run programs with either approach although different deterministic methods are used for the latter.

Photos & Wires
From a time standpoint, the first pics were taken immediately after the SkyScraper stack was built. This is different from the BASIC Stamp Supercomputer project that had hundreds or thousands of wires protruding. The first UltraSpark 40 design is much more lean and intentionally wired as compact as possible. At higher frequencies there is a consideration to keep wires shortened, and minimal. With overclocking and 100MHz frequencies, such wiring efficiency becomes more important.

Overclocking
I'm experimenting with overclocking and have some very good results. I've found that use of solderless breadboards is possible if the clock is not raised over 100 MHz. Wires need to be kept non looping and minimal length with proper gauge selected. Overclocking raises the current consumption dramatically. Be prepared to use a power supply that can handle the increased amps. If machines are built massively bigger than the UltraSpark 40 with overclocking, they may need to tap into adjacent rooms for power, like a kitchen and a living room for example.

Cryogenic SuperCooling
There's ongoing research and some experiments being developed for supercooling to around dry ice temperatures. Peltier devices are favored though other methods are being tested. More equipment is needed to make this self running. The Cryogenic chamber can be approximately the same as that of the ST4 Astronomical CCD Super Cooled Imaging camera sensor chip. Grouping chips and enlarging the chamber will benefit future designs. I may introduce Virtual CCD Cooling concepts across the Propeller chip.

Color Coding
Colored wire is coded throughout so if a wire falls off, it can easily be remedied by color grouping techniques.

Mixing Art & Science
As some have pointed out, projects may appear have a degree mix of art and science. It may be the way the photos are composed or the construction style of the device, or the way that it can be re-purposed. It's perfectly valid to style your projects by morphing together art and science.

Predecessor Machines
There are at least sixteen machines built before the UltraSpark 40. Each of these machines was utilized to test functions and lay the groundwork for a larger machine. Each project was recycled into the next larger machine. The list will be updated with historical data in a future post.
Demo Board for confirmation
HYDRA front end for mouse, keyboard, TV, VGA
PEK 1 prop on breadboard
2-Prop-Experiment 2 props, 1 PEK, 1 on same breadboard
Spark 2 2 props, 1 Proto Board, one in parallel, recycled for Spark 4
PIGGY-TWINS 2 props, one piggybacked on another
Dueling Breadboards 2 props, one on ea., f/interface tests
Spark 4 Tiny Tim 4 props 2 proto bds w/2 props on ea
Spark 5 5 props, 5 stacked proto boards, Spark 6 forerunner
Spark 6 6 props 3 proto boards 2 props on ea board, led to Spark 8
Spark 8, Tertiary ADJUNCT 8 props 4 proto boards w/2 props on ea
Propalot - 10 props on solderless breadboard, led to Spark 10
Spark 10, 10 props 5 protos 10 props total, Twelvenator forerunner
Twelvenator aka Board of Twelve, 12 props, green board
UltraSpark 15 15 props, interrupted stack Proto Boards
Tertiary 20 20 props, 15 proto boards stacked 5 props, photos
UltraSpark 20 20 props stacked, photos
MLEPS 25 props, boards/breadboards, stripped for UltraSpark 40
Additional Results & Ongoing Studies
Banking experiments
Loading techniques
New inventions (BIN)
PWR management
Horizontal forms
Adjunctive considerations
Forms of communication using LEDs (cheap)
Exploring advantages of FP processing and analysis
BUS expansion
Additional designs with COUNTERs
Chunk space signaling
How a neuron can be implemented
Recycling
(New!) Additions to the US40
Floating Point
Hybrid Integer and FP Mode
Addtl. Processor Functions
Addtl. States in Trinary
Speed Test
Languages

Guest Commentator
It is with great honor that we have comments from Forest Godfrey, a man who has worked on building the world's fastest Jaguar Supercomputer.

http://forums.parallax.com/showthread.php?t=125674&page=2

I like the "supermicrocontroller" name to describe Humanoido's tower. It's phenomenal at doing the things microcontrollers do well: controlling GPIO pins, talking low-level hardware protocols, controlling screens, etc. If your goal is to create a cool piece of microcontroller hardware that nobody else has and can control massive amounts of I/O, the Prop Tower is pretty darn sweet. I've been working to get us to use a Prop in our control paths. Forest Godfrey

July International Propeller Trophy Award

Dr_Acula

  












Recognizing outstanding individuals
in Propeller computing science - July 2013

DR_ACULA
WINNER OF

HUMANOIDO LAB'S

INTERNATIONAL PROPELLER
TROPHY AWARD

for outstanding contributions in the field of Propeller Computing Science & contributing science to Humanoido Laboratories

There's undoubtedly a time an a place for everything in the universe. Humanoido Labs has taken this time to recognize outstanding individuals in the field of Propeller Computing Science as directly observed by the Lab.

While we want to recognize numerous people, we can only make presentations one at a time. The person chosen for this award is not only gifted with great intelligence and wisdom, but is also tempered with patience, kindness, helpfulness, friendliness, and has qualities of being polite, courteous, civil, and respectful towards others - qualities which are sometimes difficult to find in today's fast competitive world.

Dr_Acula is known for his innovative Propeller projects, his brilliant mind, volunteering and sharing an abundance of technical information, being generous, and going out of his way to help others. Dr_Acula has clever thinking and has developed new ways of looking at the world and has made the world a better place for others. In particular, pointing out key references to the operation of the human brain in terms of processing power and various types of computational speed has mounted enough additional points to win this months award.

HOME PAGE
http://www.smarthome.jigsy.com/propeller

Propeller Spin Brain Part 2

MORE ABOUT THE SPIN BRAIN
PROPELLER SPIN BRAIN PART 2
"The Spinning Brain"
Continuing with our previous edition about the Spin Brain, we will look at five Parallax Propeller chips connected together to make a new type of processing machine, examining more elements and specs about this cute little machine.

In this Edition of The Spinning Brain, we will cover
- 5 Chip Inventory
- Processors
- Speed Units
- Related Links

CHIP INVENTORY
Five chips provide for the following useful elements of functional inventory:

5 Chip Inventory
* Five AI individuals (5 chips)
* 40 Deterministic Cores (5x8 Cogs)
* 160 GPIO Pins (5x32)
* 160K RAM (5x32K)
* 160K ROM (5x32)
* 80 Counters (5x16)
* 40 Video Generators (5x8)
* 13,600 MIPS (5x2720 Theoretical)*
* 160 Hard Processors (5x32)
* 5,000 Vprocessors (5x1,000)
* 5,160 Total Processors (5,000+160)
* SPIN, PASM Programming Languages

PROCESSORS
Each Cog is a RISC processor and each chip has eight. Each counter is a processor with exactly one instruction: a conditional ADD. A chip has 16 counters. Each video generator is a processor with one instruction: a Shift by one or two. A chip has eight video generators.

Processors per Chip
08 Cogs
16 Counters
08 Video Generators
32 Total Processors per chip 

SPEED UNITS
MIPS  - Millions instructions per second
DFLOP - D stands for ten      (DECA)
HFLOP - H stands for hundred  (HECTO)
KFLOP - K stands for thousand (KILO)
MFLOP - M stands for million  (MEGA)
GFLOP - G stands for billion  (GIGA)
TFLOP - T stands for trillion (TERA)

13,600 MIPs is 13,600,000,000 IPS or 13.6 billion instructions per second, related to 13.6 GFLOPs. In going from 5 chips to 100: 20x13.6=272 GFLOPS.*

* Note this is a relative theoretical comparison from one Propeller chip to a series of Propellers within the contextual definitions we have established for one chip, and is not intended as a comparison to other machines with other designs.

LINKS
Spin Brain 
Supertronic Spin Brain
FLOPS
Parallax
Propeller Info
Propeller Chip

Transposition Era

Big Brain
TRANSPOSITION ERA
The Big Brain has entered into the Transposition Era, a new time period in which more powerful and more massive thinking machines are being built.

links
http://humanoidolabs.blogspot.tw/2012/01/big-brain-era.html

Emerging Worlds of Massive Transposition Machines

SuperTronic Brain

Emergence of a New Brain
THE SUPERTRONIC BRAIN
Development Name SuperTronic 12

SuperTronic Brain prototype with Prop Plug ready for download

 




















* Robot Power Brain

* Autonomous Life Form

* Independent Function

* Academic Persuit

* Fun Hobby Experiments

* New Techniques Exploration

* Algorithm Development

* Intellectual Machine

* Parallel Trainer

* Learner 

THE RISING GIANT "BLUE MOON" event this week ushered in a new extremely powerful SuperTronic Brain. The SuperTronic Brain Machine is a living entity with 12,384 total computer processors on one board. It's designed for new applications that most likely no one has thought about.

THE NEXT GENERATION IS HERE! The SuperTronic takes the previous enhancements of the 32-Bit Parallax Propeller chip to the next level, incorporating more chip internal hard processors, new definitions of relative operating speed, various levels and types of processors, and a multi-chip hybrid deterministic parallel and hyper threaded environment and platform.

INTRODUCTION
The SuperTronic is physically smaller than the Big Brain, residing its power all on one board, with programming in Propeller Assembly and SPIN. C or C++ (with Parallax Propeller GCC) is an option as are many other languages (up to 240 programming languages, see the link below). GCC runs faster than Spin and exceeds the per chip 32K memory limit size by using the Large Memory Module LMM and Extended Memory Module (XMM). This opens up Float and the new machine also runs the new DISP language made up of DAs or Distributed Algorithms. As a parallel microcontroller machine, it can operate up to 384 ports simultaneously in either input or output modes and can be tri-stated for special applications.

OVERVIEW
The battery operated portable brain has access to distributed 768K RAM/ROM and 384K EEPROM. Relative speed of the SuperTronic is a blazing 32,640 MIPS or about 33 billion instructions per second. Including four different types of processors in high densities, the brain can offer solutions for a neural injection distribution platform.

SPECIAL TECHNIQUES

Such a platform can also handle many of the Lab's long term developed original techniques and inventions.

Cubing
Internal Transforming
Internal Teleportation
Nanites
Partitions

MIMs (Machines in Machines)

Cloning
Assimilation
Radio Brain Thought Monitor
Brain Wave Monitor BWMs
ParaP (PARP) Parallel-Parallel
Jump Over Communications
At-Once Particulator
Electronic Brain Fluid
Hyper Neural Threading
Brain Channeling
No Parts Invention
Intellectual Surfing
Shape Shifting
Internal Swarming
Neural Injection
Que Messaging
OffSetting
Arraying
Hybriding
Wire Sharing
Soft Wiring
Power Reduction
Intellectual Docking
Wireless Remote Control

KIT DETAILS
Retail cost for Propeller chips to populate the board are available in the USA from Parallax at under $100 for twelve Propeller chip "socket installments." The SuperTronic Brain Kit includes a Green Board. Additional parts required for assembly include Parallax P8X32A 32-bit Propeller chips, LEDs, decoupling capacitors, dropping resistors, sockets, and EEPROMs.

PERIPHERALS
Optional brain hookup includes a terminal, LCD, TV, Mouse, Game Paddle Controllers and Keyboard. A small kit of resistors and a socket is all that's required to add VGA output. Speech requires earphones.

The SuperTronic Brain could also be applied to many of the Big Brain peripherals.

Universe Penetrator
Adjunctive Array
Multi Mag Slider
Slipstream Drive
Transporter
AntiVortex Device
Robotic Reel
Micro RADAR
VARF
Walking Secondary
Intelligent Mirror
MLT
$5 Quadcopter
Pinhole Machine
Waterdrop Devices
ULT Ultra Large Telescope
NULT New Ultra Large Telescope 
GT Genius Telescope

APPLICATIONS
One aspect of this powerful brain would include functioning as the work horse in a private space program. It fits telemetry, data processing and number crunching, and has access to autonomous guidance routines and optical management.

SOFTWARE
In House Lab Software tailored for this one board solution is tentatively expected to include the Propeller Brain RTOS Real Time Operating System (The SOS is a SuperTronic Operating System.), a Multi-Chip Parallel Loader, a Processor Enhancer, Multiple Threader, Timing Manager, Enumerator, and details about the Cloner. Additional software is found at the Parallax OBEX.

MANUAL & STACKING
The machine assembly manual will use a verbal (word) schematic so construction is ultimately simple. Stacking is possible. With ten boards, the processor count equals 123,840 and the speed rises to 326,400 MIPS, though power increases based on operating mode.

CONSTRUCTION
Construction as seen in the photo shows the first prototype (working) assembled on a solderless breadboard with the first test wiring. At right is a Prop Plug ready for downloading software. This config has an accurate crystal controlled time base and a 32K EEPROM to store programs. Also visible is the electrolytic filter and 10nf decoupler capacitors. The prototype shown has two extra temporary driver chips which will be removed after testing.

PROGRAMMING LANGUAGES

Recommended programming languages include Propeller Assembly and SPIN. The Propeller chip has access to approximately 232 programming languages, versions & variations along with five programming language converters and methods, for almost any kind of experimenting and academic persuit. (see link below)

LINKS
Ultimate List of Propeller Languages
http://humanoidolabs.blogspot.tw/2012/03/ultimate-list-of-big-brain-languages.html

Blue Moon
http://earthsky.org/astronomy-essentials/when-is-the-next-blue-moon